• Nvis Technology
  • Nvis Technology
  • Nvis Technology
  • Nvis Technology
  • Nvis Technology
  • Nvis Technology
  • Nvis Technology
  • Nvis Technology
Nvis Technology

Head Office

141-A, Electronic complex, Pardesipura,Indore - 452010 India

Phone: +91 73899 00887 , +91 98932 70303

Email:info@nvistech.com

Request a Quote

Looking for a quality and affordable builder for your next project?




    Nvis Technology

    Toll Free

    +91 73899 00887

    We are happy to meet you during our working hours. Please make an appointment.

    • Monday-Saturday: 9:00 AM - 5:30 PM (IST)
    • Sunday: Closed

    Experimentation with De-Morgan`s Theorem

    Nvis 6553

    Product Description

    Experimentation with De-Morgan`s Theorem Nvis 6553 is an elite training system for the digital laboratories. It is useful in understanding the basic concept of De-Morgan`s Theorem. This trainer describes both the De-Morgan`s Theorem statements in two separate sections so it is very easy for students to understand both the statements separately.

    The training system is designed in such a way that for performing any experiment students have to connect the links by patch cords, so it is very helpful for students to learn step by step implementation of De- Morgan`s Theorems. Attractive input and output sections are provided on trainer in such a manner so that multiple experiments can be performed simultaneously.

    Nvis 6553, Experimentation with De-Morgan`s Theorem is an ideal platform to enhance education, training, skills & development amongs our young minds.

    Product Features

    • Exclusive and compact design
    • Easy explanation of both the De-Morgan`s theorem statements
    • +5V SMPS Adaptor provided with the trainer for power supply
    • Designed by considering all the safety standards
    • Provided with an extensive manual
    • A low cost training system
    • Online product tutorial
    Scope of Learning
    • >Designing of NOT gate using NAND gate
    • Designing of AND gate using NAND gate
    • Designing of OR gate using NAND gate
    • Designing of NOT gate using NOR gate
    • Designing of AND gate using NOR gate
    • Designing of OR gate using NOR gate