• Nvis Technology
  • Nvis Technology
  • Nvis Technology
  • Nvis Technology
  • Nvis Technology
  • Nvis Technology
  • Nvis Technology
  • Nvis Technology
Nvis Technology

Head Office

141-A, Electronic complex, Pardesipura,Indore - 452010 India

Phone: +91 73899 00887 , +91 98932 70303

Email:info@nvistech.com

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    Nvis Technology

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    +91 73899 00887

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    • Monday-Saturday: 9:00 AM - 5:30 PM (IST)
    • Sunday: Closed

    Experimentation with Universal Gates-Nand and Nor

    Nvis 6552

    Product Description

    Experimentation with Universal Gates-Nand and Nor Nvis 6552 is an elite training system for digital laboratories. It is useful for understanding of the basic concepts and functioning of universal gates as well as their use as other logic gates. This trainer describes the formation of AND, OR, NOT, NAND, NOR, XOR and XNOR gates using NAND and NOR gates which are called universal gates.

    The training system is designed in a way that for performing any experiment students have to connect the links by patch cords, thereby enabling students to learn step by step design of each gate using universal gates. Attractive input and output sections are provided on trainer in a manner that multiple experiments can be performed simultaneously.

    Nvis 6552, Experimentation with Universal Gates-Nand and Nor is an ideal platform to enhance education, training, skills & development amongs our young minds.

    Product Features

    • Exclusive and compact design
    • Straight forward representation of Universal Gates
    • +5V SMPS adaptor provided with the trainer for power supply
    • Designed by considering all the safety standards
    • Online product tutorial
    • Low cost trainer including illustration of logic gates design using universal gates
    Scope of Learning
    • Designing of NOT gate using NAND gate
    • Designing of AND gate using NAND gate
    • Designing of OR gate using NAND gate
    • Designing of NOT gate using NOR gate
    • Designing of AND gate using NOR gate
    • Designing of OR gate using NOR gate